LAN91C100FD REV. D
FEAST Fast Ethernet
Controller with Full
Duplex Capability
Data Brief
PRODUCT FEATURES
„
Dual Speed CSMA/CD Engine (10 Mbps and 100
Mbps)
„
„
„
Built-In Transparent Arbitration for Slave Sequential
Access Architecture
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„
Compliant with IEEE 802.3 100BASE-T Specification
Flat MMU Architecture with Symmetric Transmit and
Receive Structures and Queues
Supports 100BASE-TX, 100BASE-T4, and 10BASE-
T Physical Interfaces
MII (Media Independent Interface) Compliant MAC-
PHY Interface Running at Nibble Rate
„
„
„
„
32 Bit Wide Data Path (into Packet Buffer Memory)
Support for 32 and 16 Bit Buses
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„
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MII Management Serial Interface
Seven Wire Interface to 10 Mbps ENDEC
EEPROM-Based Setup
Support for 32, 16 and 8 Bit CPU Accesses
Synchronous, Asynchronous and Burst DMA
Interface Mode Options
Full Duplex Capability
„
128 Kbyte External Memory
ORDER NUMBER(S):
LAN91C100-FD 208-PIN QFP PACKAGE
LAN91C100-FD-SS FOR 208-PIN QFP LEAD-FREE ROHS COMPLIANT PACKAGE
LAN91C100-FD FOR 208-PIN TQFP PACKAGE
LAN91C100-FD-ST FOR 208-PIN TQFP LEAD-FREE ROHS COMPLIANT PACKAGE
SMSC LAN91C100FD REV D
PRODUCT PREVIEW
Revision 1.0 (09-22-08)
FEAST Fast Ethernet Controller with Full Duplex Capability
General Description
The LAN91C100FD is designed to facilitate the implementation of first generation Fast Ethernet
adapters and connectivity products. For this first generation of products, flexibility dominates over
integration. The LAN91C100FD is a digital device that implements the MAC portion of the CSMA/CD
protocol at 10 and 100 Mbps, and couples it with a lean and fast data and control path system
architecture to ensure the CPU to packet RAM data movement does not cause a bottleneck at 100
Mbps.
Total memory size is 128 Kbytes, equivalent to a total chip storage (transmit plus receive) of 64
outstanding packets. The LAN91C100FD is software compatible with the LAN9000 family of products
and can use existing LAN9000 drivers (ODI, IPX, and NDIS) in 16 and 32 bit Intel X86 based
environments.
Memory management is handled using a unique MMU (Memory Management Unit) architecture and a
32-bit wide data path. This I/O mapped architecture can sustain back-to-back frame transmission and
reception for superior data throughput and optimal performance. It also dynamically allocates buffer
memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host CPU
from performing these housekeeping functions. The total memory size is 128 Kbytes (external),
equivalent to a total chip storage (transmit and receive) of 64 outstanding packets.
FEAST provides a flexible slave interface for easy connectivity with industry-standard buses. The Bus
Interface Unit (BIU) can handle synchronous as well as asynchronous buses, with different signals
being used for each one. FEAST's bus interface supports synchronous buses like the VESA local bus,
as well as burst mode DMA for EISA environments. Asynchronous bus support for ISA is supported
even though ISA cannot sustain 100 Mbps traffic. Fast Ethernet could be adopted for ISA-based nodes
on the basis of the aggregate traffic benefits.
Two different interfaces are supported on the network side. The first is a conventional seven wire
ENDEC interface that connects to the LAN83C694 for 10BASE-T and coax 10 Mbps Ethernet
networks. The second interface follows the MII (Media Independent Interface) specification draft
standard, consisting of 4 bit wide data transfers at the nibble rate. This interface is applicable to 10
Mbps or 100 Mbps networks. Three of the LAN91C100FD’s pins are used to interface to the two-line
MII serial management protocol. Four I/O ports (one input and three output pins) are provided for
LAN83C694 configuration.
The LAN91C100FD is based on the LAN91C100 FEAST, functional revision G modified to add full
duplex capability. Also added is a software-controlled option to allow collisions to discard receive
packets. Previously, the LAN91C100 supported a “Diagnostic Full Duplex” mode. Under this mode
the transmit packet is looped internally and received by the MAC. This mode was enabled using the
FDUPLX bit in the TCR. In order to avoid confusion, the new, broader full duplex function of the
LAN91C100FD is designated as Switched Full Duplex, and the TCR bit enabling it is designated as
SWFDUP. When the LAN91C100FD is configured for SWFDUP, it’s transmit and receive paths will
operate independently and some CSMA/CD functions will be disabled. When the controller is not
configured for SWFDUP it will follow the CSMA/CD protocol.
SMSC LAN91C100FD REV D
3
Revision 1.0 (09-22-08)
PRODUCT PREVIEW
FEAST Fast Ethernet Controller with Full Duplex Capability
Block Diagram
SERIAL
EEPROM
Address
10 Mb
Interface
ARBITER
DIRECT
BUS
Data
MEMORY
INTERFACE
ACCESS
100
Media
MEDIA
UNIT
Control
ACCESS
Indepe ndent
Interface
MEMORY
MANAGEMENT
UNIT
CONTROL
RD
FIFO
WR
FIFO
RAM
25 MHz
Figure 1 LAN91C100FD Block Diagram
Revision 1.0 (09-22-08)
4
SMSC LAN91C100FD REV D
PRODUCT PREVIEW
FEAST Fast Ethernet Controller with Full Duplex Capability
Package Outlines
Figure 2 208 Pin QFP Package Outline
Table 1 208 Pin QFP Package Parameters
MIN
NOMINAL
MAX
REMARK
A
A1
A2
D
~
~
4.07
0.5
Overall Package Height
Standoff
0.05
3.17
30.35
27.90
30.35
27.90
0.09
0.45
~
~
~
3.67
30.85
28.10
30.85
28.10
0.20
0.75
~
Body Thickness
X Span
~
D1
E
~
X Body Size
~
Y Span
E1
H
~
Y body Size
~
Lead Frame Thickness
Lead Foot Length
Lead Length
L
0.60
L1
e
1.30
0.50 Basic
Lead Pitch
o
o
q
0
~
~
~
~
~
7
Lead Foot Angle
Lead Width
W
R1
R2
ccc
0.10
0.08
0.08
~
0.30
~
Lead Shoulder Radius
Lead Foot Radius
Coplanarity
0.25
0.08
Notes:
1. Controlling Unit: millimeter.
2. Tolerance on the true position of the leads is ± 0.04 mm maximum.
3. Package body dimensions D1 and E1 do not include the mold protrusion.
Maximum mold protrusion is 0.25 mm.
4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane.
5. Details of pin 1 identifier are optional but must be located within the zone indicated.
SMSC LAN91C100FD REV D
5
Revision 1.0 (09-22-08)
PRODUCT PREVIEW
FEAST Fast Ethernet Controller with Full Duplex Capability
Figure 3 208 Pin TQFP Package Outline
Table 2 208 Pin TQFP Package Parameters
MIN
NOMINAL
MAX
REMARK
A
A1
A2
D
~
~
1.60
0.15
1.45
30.20
28.10
30.20
28.10
0.23
0.75
~
Overall Package Height
Standoff
0.05
1.35
29.80
27.90
29.80
27.90
0.09
0.45
~
~
~
Body Thickness
X Span
~
D1
E
~
X Body Size
~
Y Span
E1
H
~
Y body Size
~
Lead Frame Thickness
Lead Foot Length
Lead Length
L
0.60
L1
e
1.00
0.50 Basic
Lead Pitch
o
o
q
0
~
0.22
~
7
Lead Foot Angle
Lead Width
W
R1
R2
ccc
0.17
0.08
0.08
~
0.27
~
Lead Shoulder Radius
Lead Foot Radius
Coplanarity
~
0.20
0.08
~
Notes:
1. Controlling Unit: millimeter.
2. Tolerance on the true position of the leads is ± 0.04 mm maximum.
3. Package body dimensions D1 and E1 do not include the mold protrusion.
Maximum mold protrusion is 0.25 mm.
4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane.
5. Details of pin 1 identifier are optional but must be located within the zone indicated.
Revision 1.0 (09-22-08)
6
SMSC LAN91C100FD REV D
PRODUCT PREVIEW
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